1. Field of the Invention
The present invention relates to the design of essentially digital systems and components thereof as well as to the essentially digital systems made in accordance with the design.
2. Description of the Related Technology
It is clear that in sub-100 nm technology nodes, the importance of interconnect on system delay and energy consumption will become dominant (see e.g. [5,6,9,12,8] and SPT research).
If this problem is viewed locally, from the process technology and circuit design point of view, this has been perceived for quite some time as one of the red brick walls for further progress in improved density, performance and reduced system energy. But when also the system and architecture view point are included several viable though usually not simple solutions exist to avoid that wall. This is especially true in the large market of embedded energy-sensitive systems as encountered in ambient multi-media, communication terminals and protocols, and consumer electronics in general.
What really counts in such systems is, namely, not the achievable maximal clock frequency but the overall system throughput. Moreover, usually this throughput is lower bounded but increasing it beyond that bound is not that useful. Hence, overall system timing is mostly a constraint (hard or soft) and the cost functions to optimize are system cost (in Dollars or Euro's) and system energy for a given functionality. In quality-aware (QoS) systems, the level of desired or achievable quality is another important system parameter. In order to achieve a better trade-off between all these different aspects for a given application, a complex exploration space has to be traversed. That has been proven to be nearly infeasible for the complexity of today's applications. Hence, the need for system design technology support, i.e. both systematic methodologies and appropriate supporting design tools wherever needed to keep the design time reasonable. Worldwide, many contributions have been made to some solutions in the last two decades. It has lead to several usable contributions for such system design technology and the research remains ongoing because despite the results achieved, many problems are still not sufficiently solved.
Up till 2001, all that research—at least in the digital domain—was performed using a (very) high-level abstraction of the underlying process technology. That abstraction, situated mostly at the parameterisable module level and partly at the standard cell level, was shown to be sufficient to arrive at good working designs already in the 80's. It has proven its worth up to today. But the advent of the wire dominated process technologies has—at least partly—broken down the validity of this abstraction. As long as transistors dominate, the predesigned circuits of the modules and standard cells could be combined without worrying too much about interconnections. Now that interconnect gradually becomes dominant, this leads to a system design problem. For the performance related aspects this is known as the timing closure problem. A similar problem exists for energy reduction because optimization at the system level has the largest impact but cannot rely on reasonably accurate energy models when the interconnect dominates.
This application domain (see above) has seen another clear trend in the past decade: most of the system energy, performance and other costs become dominated by the memories (on and off-chip) and the large communication routes. The logic islands in between become more and more negligible. One of the main reasons is that applications have become very data dominated accessing huge data sets. Another factor is the evolution of much of the memory from the board to the on-chip level.
As a result, the old system-level abstraction can be substituted by a new one, which is at least valid in the early system exploration phases: logic is mostly ignored and the memories and communication routes form the main cost factor to steer the exploration. For memories, parameterized modules can be used, even if the interconnect dominates. The internal models for these memories are heavily affected but it is still feasible to arrive at reasonable models. Several activities of ongoing research are relevant in this, such as the work of K. ltoh et al [7] and N. Jouppi et al [14], and in the group of M. Horowitz [I].
At present the number of technology related parameters in such models is quite small.